The present invention relates to a semiconductor integrated circuit (in particular, an improved semiconductor integrated circuit for testing internal circuits for failures through a scan test), a method for designing the semiconductor integrated circuit, and a storage medium in which the design program therefor is stored.
In general, it is difficult to test logic circuits constituting a semiconductor integrated circuit (among other things, logic circuits for generating clock signals, reset signals and set signals) by utilizing a scan path.
More specifically, in a conventional semiconductor integrated circuit, a clock signal generated by a logic circuit (i.e., a clock signal generator) is selected by a selector and input to a predetermined storage device such as a flip-flop during normal operation. In a scan mode, however, not the clock signal generated by the clock signal generator, but an externally supplied scan clock signal is selected by the selector and input to the storage device. Thus, in the conventional circuit, the clock signal generated by the clock signal generator is valid during the normal operation, but is invalidated in the scan mode. Accordingly, in the scan mode, it is impossible to test the clock signal generator.
In order to solve such a problem, a circuit for testing a clock signal generator and the like (herein represented by the "clock signal generator") by providing some means for monitoring the signals generated by the generator is provided and disclosed in Japanese Laid-Open Publication No. 61-234376, for example. More specifically, a selector is provided between the output of the clock signal generator and a storage device responsive to the clock signals. During the normal operation, the selector selects the clock signals generated by the clock signal generator. On the other hand, in the scan mode, the selector selects an externally provided test clock signal and provides the signal to the storage device, thereby performing a scan test. Furthermore, an external output terminal for monitoring is provided, a signal line connecting the clock signal generator to the selector is branched and the branch of the signal line is connected to the external output terminal for monitoring. In this manner, the clock signal generated by the clock signal generator is monitored at the external output terminal, thereby testing the clock signal generator.
However, the conventional circuit requires not only an external terminal for scan testing but also the external output terminal for testing the clock signal generator. Thus, the number of terminals of such a semiconductor integrated circuit is larger than that of an ordinary circuit. Particularly when the number of the clock signal generators provided is large, the number of the external output terminals for testing is also large. In view of the strict limitation recently imposed on the number of terminals of a semiconductor integrated circuit, such a configuration cannot be implemented in some cases. In addition, since the conventional circuit requires the signal line connecting the clock signal generator to the external output terminal for testing, the size of the circuit is adversely increased. Especially when the number of the clock signal generators provided is large, the number of the signal lines also increases correspondingly, thereby further increasing the circuit size.
In order to eliminate such a problem, according to the technique disclosed in Japanese Laid-Open Publication No. 62-169066, for example, a selector is disposed between a logic circuit and a storage device, such as flip-flop, for storing the output of the logic circuit. The selector selectively provides the clock signal, generated by the clock signal generator, to the storage device. In the scan mode, the selector selectively switches the supply of the output of the logic circuit and the clock signal generated by the clock signal generator. The input to the storage device, i.e., the output of the logic circuit or the clock signal provided from the clock signal generator, is monitored at a scan-out terminal. In such a manner, the clock signal generator can be tested while eliminating the external output terminal, through which the output signal of the clock signal generator is output and monitored externally, and the signal line leading to the output terminal.
However, the above-identified publication fails to disclose a specific controller for controlling the selector (corresponding to the select signal output circuit of the present invention). Thus, no detailed information enabling appropriate control and switching of the selector during the normal operation and scan modes is provided by the publication.